THis invention is related generally to flip-flop circuits and is related more specifically to set-reset flip-flops using logic elements and time delay means.
Set-reset flip-flop circuits are known. They generally comprise analog devices interconnected with combinations of resistors and capacitors of digital gates interconnected with combinations of resistors and capacitors. In typical flip-flop operation there are two input terminals and two output terminals. One input terminal is called a "set" input and the other input terminal is called a reset input. Typically the output terminals are complementary, that is, when one is at a high voltage state other of necessity is at a low voltage state. By supplying a trigger signal to an appropriate input terminal, the two output terminals of the flip-flop will reverse voltage states provided the input signal had attained a proper voltage level to begin with. Furthermore, subsequent provisions of the same signal to the same terminal will not cause a further shift in the status of the outputs of the flip-flop unless an intervening signal is supplied to the other input terminal. In the case of a digital flip-flop an input terminal actuated by providing a digital "one" level thereto. The provision of a digital "zero" level will not cause a shift in states of the outputs of the flip-flop. Typically interconnecting latching circuitry is provided for gates of a digital flip-flop circuit. The latching apparatus comprises a feedback circuit which assures that a change in output states, once initiated by a proper triggering signal, will be completed even if the triggering signal quickly disappears. In the logic flip-flop circuit the latching system provides an appropriate digital signal to a gate. This prevents the output terminals of the flip-flop from changing state on subsequent pulses to the same gate without an intervening signal being applied to the other input terminal. Because of the nature of the flip-flop circuit, a relatively fast pulse, that is, one which quickly appears and then disappears, on an appropriate input terminal can cause a relatively long-term change in status for the output terminals, at least until another input terminal is properly actuated. However, it is recognized that random noise, which may exist on the input terminal because of electromagnetic phenomenon or anomalies of the power supply regulation can cause undesired switching of the outputs of the flip-flop. This is because the flip-flop cannot distinguish between a random, undesired, relatively fast noise pulse and a true triggering pulse. It would be desirable therefore if means could be provided for distinguishing between noise signals and true triggering signals for a flip-flop.